1. Field of the Invention
The present invention relates to a semiconductor chip and a wiring board wherein external electrodes on both sides of a semiconductor substrate are electrically connected by means of conductive patterns formed so as to follow the sides of the semiconductor substrate and the manufacturing process thereof as well as a semiconductor device that uses the semiconductor chip thereof.
2. Description of Prior Art
In recent years together with the miniaturization and the increased performance of electronics, as represented by computers and communication apparatuses, miniaturization, increased density and increased speed have become required for semiconductor devices. Therefore, a multi-chip type semiconductor device has been proposed wherein a plurality of semiconductor chips are mounted on a wiring board so as to form a module and miniaturization and higher density have been achieved.
In the following, several different modes of conventional semiconductor devices are described.
FIGS. 60 to 64 are cross section views showing conventional semiconductor devices.
First, as shown in FIG. 60, a plurality of semiconductor chips 2 are mounted on a wiring board 1 according to a flip chip system so that electrodes of the semiconductor chip 2 and connection electrodes of the wiring board 1 are electrically connected through metal bumps 3 and a plurality of semiconductor chips are mounted on one wiring board by being arranged in a plane.
Next, as shown in FIG. 61, a plurality of semiconductor chips 5 are layered on a wiring board 4 wherein electrodes of respective semiconductor chips 5 and connection electrodes of the wiring board 4 are electrically connected through metal wires 6 so that the mounting area of semiconductor chips relative to the wiring board becomes smaller in comparison with the mode where semiconductor chips are arranged in a plane.
In addition, as shown in FIG. 62, the surfaces of two semiconductor chips 7 where electrodes are formed are made to face each other and electrodes of respective semiconductor chips 7 are electrically connected through metal bumps 8 so as to have a layered boardless structure.
In addition, as shown in FIG. 63, a plurality of semiconductor devices wherein semiconductor chips 9 are mounted on wiring boards 11 via metal bumps 10 in a flip chip system are layered so that wires of the respective wiring boards 11 are electrically connected through metal bumps 12.
Several different modes of conventional semiconductor devices are described in the above and all of these conventional semiconductor devices implement semiconductor devices formed of a plurality of a semiconductor chips which have a mode wherein a plurality of semiconductor chips are mounted on a wiring board in a plane, a mode wherein a plurality of semiconductor chips are layered on a wiring board, a mode wherein surfaces of semiconductor chips where circuits are formed are made to face each other so as to be electrically connected through metal bumps and a mode wherein mounting bodies formed of semiconductor chips mounted on wiring boards are layered.
In addition, since electrodes are formed only on one side of a semiconductor chip which forms each semiconductor device, semiconductor chips are electrically connected to each other by using metal wires or boards in the case that semiconductor chips are layered.
FIG. 64 is a cross section view of a semiconductor device using a conventional resin wiring board.
As shown in FIG. 64, one, or a plurality, of semiconductor chips 2 are mounted in a plane according to a flip chip system on a resin wiring board 1 formed of a complex material, including an epoxy resin, wherein surface electrodes of the semiconductor chip(s) 2 and connection electrodes on the surface of the resin wiring board 1 are electrically connected through metal bumps 3. Furthermore, connection electrodes on the rear side of the resin wiring board 1 are electrically connected to wires of a mother board 405 by means of solder balls 404. Here, connection electrodes on both sides of the resin wiring board 1 are electrically connected through conductive patterns formed on the inner walls of through holes (not shown) which pass through the inside of the resin wiring board 1.
In this manner, the semiconductor chip(s) 2 is(are) not directly mounted on the mother board 405 but, rather, the resin wiring board 1 is inserted between the semiconductor chip(s) 2 and the mother board 405 in the structure.
However, the respective modes of the conventional semiconductor devices where a plurality of semiconductor chips are layered have the problems as follows.
First, as shown in FIG. 60, since a plurality of semiconductor chips 2 are arranged on the wiring board 1 in a plane, the area of the wiring board 1 needs to be, at least, larger than the sum of the areas of the plurality of semiconductor chips 2 and the larger is the number of mounted semiconductor chips 2, the larger must be the area of the wiring board 1.
In addition, in the semiconductor device shown in FIG. 61, it is necessary to expose electrodes for connecting the metal wires 6 which make an electrical connection with the wires of the wiring board 4 on the upper surface of a semiconductor chip 5 every time that the semiconductor chip 5 is layered and, therefore, the semiconductor chip which is far away from the board becomes small. Accordingly, it is impossible to layer semiconductor chips of the same size and the total length of the metal wires 6 becomes longer when the number of layered semiconductor substrate 5 increases and, therefore, there is a problem that the wire length becomes long.
In addition, in the semiconductor device shown in FIG. 62, it is impossible to layer three or more semiconductor chips 7 and, therefore, there is a limit in the function as a semiconductor device.
In addition, in the semiconductor device shown in FIG. 63, since it is necessary to provide wiring boards 11 between a plurality of semiconductor chips 9, there is problem that the thickness of the semiconductor device becomes large after the layering of the semiconductor chips.
As described above, in the conventional semiconductor devices, the mounting area becomes great in the case that a plurality of semiconductor chips are arranged in a plane, it is impossible to layer semiconductor chips of the same size because of the necessity of providing electrodes for the connection with metal wires, the number of layered semiconductor chips is limited, the functions as a semiconductor device are limited and the thickness of the semiconductor device becomes large due to the structure wherein boards are provided between the layered semiconductor chips and, therefore, it is difficult to achieve miniaturization, improved performance and increased speed.
In addition, the changes in characteristics due to temperature and humidity of a resin wiring board using a complex material, including an epoxy resin, are greater than the changes in the characteristics of a semiconductor chip and, in particular, there is a significant difference in the coefficient of thermal expansion between silicon which is the basic material of a semiconductor chip and an epoxy resin-based complex material and, therefore, a large amount of stress occurs in the connection part between a semiconductor chip and a resin wiring board and, therefore, there is a risk that the connection part will be broken.
Furthermore, since the flatness of a resin wiring board is not of a sufficient degree in comparison with a semiconductor chip, in a flip chip system wherein a semiconductor chip is directly connected to a resin wiring board there is a problem that the electrical connection is not stable between metal bumps formed on the electrodes of a semiconductor chip and connection electrodes of a resin wiring board.
In addition, since the dimension precision of the wires formed on a resin wiring board is not sufficient in comparison with the dimension precision of a semiconductor chip, positional shift occurs in connection parts between the surface electrodes of a semiconductor chip and connection electrodes of the resin wiring board so as to cause a defective connection.
Furthermore, since semiconductor chips are mounted on the resin wiring board in a plane in the structure, it is impossible to make the area of the resin wiring board smaller than the total area of the mounted semiconductor chips and, therefore, there is a problem that the larger the number of mounted semiconductor chips is, the larger the area of the resin wiring board is.
The present invention provides, in order to solve the above described conventional problems, a semiconductor chip of which the main purpose is to prevent the increase in the thickness of the semiconductor device wherein semiconductor chips are layered and in the increase of the board area as well as in the increase of the wire length between semiconductor chips even when a plurality of semiconductor chips are layered on a wiring board and provides a manufacturing process thereof as well as a semiconductor device using this semiconductor chip.
The present invention provides a wiring board using silicon as a material of the wiring board and a manufacturing process thereof in order to solve the above described conventional problems.
A semiconductor chip of this invention is a semiconductor chip characterized by having a semiconductor substrate, a first external electrode formed on a first surface of the semiconductor substrate, a second external electrode formed on a second surface of the semiconductor substrate and a through hole created in the semiconductor substrate, wherein the through hole is provided in an inclined plane formed so that the internal angle relative to the second surface is an obtuse angle and wherein the first external electrode and the second electrode are electrically connected through a conductive pattern formed so as to pass through the inner wall of the through hole and the inclined plane.
According to the semiconductor chip of this invention, implementation of a semiconductor chip becomes possible wherein electrodes on both sides are connected via the conductive pattern formed in the through hole and on the inclined plane and, therefore, the miniaturization, higher density and increased speed of a semiconductor device wherein semiconductor chips are layered become possible.
A semiconductor chip of this invention is a semiconductor chip having a semiconductor substrate, a surface electrode formed on a first surface of the semiconductor substrate and a through hole created in the semiconductor substrate, wherein the through hole is provided in the inclined plane formed so that the internal angle relative to a second surface is an obtuse angle and is characterized by comprising a first insulating layer formed on the first surface except for the surface electrode, on the inner wall of the through hole, on the inclined plane and on the second surface, a conductive pattern filled in within the through hole and formed on the first insulating layer and on the surface electrode and a second insulating layer formed so as to have an opening in a part of the surface of the conductive pattern on the first surface as a first external electrode and to have an opening in a part of the surface of the conductive pattern on the second surface as a second external electrode.
According to the semiconductor chip of this invention, by forming such a conductive pattern, an electrode between the semiconductor substrate and the conductive pattern and electrodes on both sides of the semiconductor substrate exposed through the insulating layer can be electrically connected and, since the electrode and the conductive pattern are covered with an insulating layer, electrical defects such as short circuits can be prevented and the semiconductor chip can be protected from external shock and, in addition, miniaturization, higher density and increased speed become possible.
A semiconductor chip of this invention is a semiconductor chip comprising a semiconductor substrate having a surface on which elements are integrally formed, a rear side in opposition parallel to the above surface, an inclined plane formed so as to make an acute angle relative to the above surface and a recess continuing to the inclined plane created around the periphery of said surface and provided with a first electrode formed on the above surface, a second electrode formed on the rear side and a conductive pattern for connecting the first electrode and the second electrode formed within the recess and on the inclined plane.
According to the semiconductor chip of this invention, a chip for a multi-chip semiconductor device can be gained which comprises a semiconductor substrate on which elements are integrally formed and has a surface electrode and a rear side electrode connected through a conductive pattern within a recess around the surface and on the side. Accordingly, the multi-chip semiconductor device which uses such a chip for a multi-chip semiconductor device can implement a multi-chip semiconductor device that achieves miniaturization, higher density and increased speed. In addition, a conductive pattern in the recess and a conductive pattern on the inclined plane are formed so as to be connected and, thereby, processing becomes easier and the connection area between the conductive patterns can be made broad.
A semiconductor chip of this invention is a semiconductor chip comprising a semiconductor substrate which has a surface on which elements are integrally formed, a rear surface in opposition parallel to the surface, inclined planes formed so that inclined planes and the surface make up acute angles and a recess formed around the periphery of the surface which continues to the inclined planes and which has surface electrodes connected to the elements, and is characterized by comprising a first insulating layer formed on the surface, other than on the inside walls of the recess, and on the surface electrodes, first conductive patterns formed so as to fill in the recess on which the first insulating layer is formed and formed on the surface on which the first insulating layer is formed so as to be in desired forms of wires and electrodes connected to the surface electrodes, a second insulating layer formed on the surface with openings for electrode parts of the first conductive patterns, inclined planes from which the first conductive patterns in the recess are exposed in a continuous manner around the rear surface, a third insulating layer formed on the rear surface and the inclined planes with openings of parts of inclined planes from which the first conductive patterns are exposed, second conductive patterns formed on the inclined planes and on the rear surface of the semiconductor chip where the third insulating layer is formed in desired forms of wires and electrodes connected to the first conductive patterns and a fourth insulating layer formed on the rear surface and on the inclined planes of the semiconductor chip with openings for the electrode parts of the second conductive patterns.
According to the semiconductor chip of this invention, a chip for a multi-chip semiconductor device is gained wherein the first electrodes, the second electrodes, wires for connecting the first electrodes and second electrodes by going through within the recess and on the sides are formed as conductive patterns and these conductive patterns are electrically connected to the surface electrodes and an insulating layer is formed on the surface of the conductive patterns, except for on the first electrodes and on the second electrodes, and an insulating layer is formed between the conductive patterns and the semiconductor substrate. Accordingly, the multi-chip semiconductor device using such a chip for a multi-chip semiconductor device can implement a multi-chip semiconductor device which achieves miniaturization, higher density and a higher operational speed in the same manner as in claims 1 and 2.
In addition, in the above described structure, a layered metal film is formed between the first insulating layer and the conductive patterns and between the surface electrodes and the conductive patterns.
In such a structure, by forming a layered metal film, it becomes possible to form conductive patterns by using an electrolytic plating method due to a barrier layer and a seed layer forming the layered metal film so that the diffusion of the component elements of the conductive patterns can be prevented.
In the above structure, the conductive patterns, except for at least one, are formed on the surface electrodes.
In such a structure, by using a semiconductor chip which has at least one conductive pattern that is not connected to the integrated circuit, at the time when a plurality of semiconductor chips are layered, it becomes possible to electrically connect semiconductor chips mutually, other than a particular semiconductor chip without an electrical connection to the integrated circuit of the particular semiconductor chip.
In the above structure, vertical side surfaces are formed of an insulating resin supplied to the inclined planes.
In such a structure, a comparatively thick insulating layer is formed on the second conductive patterns formed on the inclined planes and, therefore, the sides of the semiconductor chip are reinforced and the conductive patterns on the inclined planes can be securely protected.
In the above structure, the layered metal film is made up of the barrier layer and the seed layer.
In such a structure, the component elements of the conductive patterns can be prevented from diffusing by means of the barrier layer and prevention of the characteristic deterioration of the semiconductor chip can be achieved while plating of the conductive patterns becomes possible through an electrolytic plating method by providing the seed layer.
A wiring board of this invention is a wiring board of which the base material is made of silicon where in a plurality of through holes are created in the wiring board, the first conductive patterns are formed on the surface of the wiring board, through holes are created in the inclined planes formed so that the inner angles made up of the inclined planes and the rear surface of the wiring board are obtuse angles, the second conductive patterns are formed on the rear surface and on the inclined planes and the wiring board is characterized in that the first conductive patterns and the second conductive patterns are electrically connected through the third conductive patterns formed in the plurality of through holes.
According to the wiring board of this invention, because of the formation of the inclined planes, it becomes unnecessary to create deep holes so that processing time can be shortened and the cost reduction can be achieved. In addition, it becomes unnecessary to polish the silicon substrate so as to make the thickness thereof smaller, and therefore, a stable conveyance is secured.
The wiring board of this invention is a wiring board for a multi chip semiconductor device, wherein electronic parts are mounted on a wiring board which is mounted on a mother board, wherein the first conductive patterns made up of at least one layer for mounting and wiring electronic parts are provided on the surface of this silicon substrate and the second conductive patterns made up of at least one layer having electrodes for being mounted on the mother board are provided on the rear surface of the silicon substrate and wherein the wiring board is characterized in that the first conductive patterns and the second conductive patterns are electrically connected through the third conductive patterns formed on the sides of the silicon substrate.
According to the wiring board of this invention, a wiring board made of silicon can be gained which has the first conductive patterns for mounting and wiring electronic parts on the top surface and the second conductive patterns for providing electrodes on the rear surface which are used to mount the wiring board on a mother board and wherein these first conductive patterns and second conductive patterns are electrically connected through the third conductive patterns formed on the sides.
This silicon wiring board does not have a formation change due to humidity and since it is formed of silicon which is the same as the semiconductor chips and the formation changes such as expansion or shrinkage due to temperature change are the same as of the semiconductor chips, the flatness is high because of the formation by polishing, dimension precisions of the electrode positions are high and it is possible to narrow the pitch of the connection electrodes at the same level as the semiconductor chips and to increase the density of the wiring.
Accordingly, the multi chip semiconductor device using such a silicon wiring board has a high reliability by reducing stress on the connection parts of metal bumps, improves the stability of the connections because of the flatness and dimension precision of the wiring board and makes the increase of the wiring density possible at the level that a resin wiring board cannot achieve so that miniaturization, a higher density and a higher operational speed can be implemented.
The wiring board of this invention is a wiring board for a multi chip semiconductor device wherein electronic parts are mounted on a wiring board which is mounted on a mother board and the wiring board has a silicon substrate made of silicon wherein sides are formed so that the sides and the surface of the wiring board form acute angles and a recess is formed around the top surface and the wiring board is characterized by comprising the first conductive patterns made up of at least one layer being formed on the top surface and within the recess of the above silicon substrate and having electrodes and the second conductive patterns made up of at least one layer being formed on the rear surface and on the sides of the silicon substrate, being connected to the first conductive patterns and having electrodes.
According to a wiring substrate of this invention, a wiring board made of silicon is gained which has the first conductive patterns on the top surface and the second conductive patterns on the rear surface wherein the first conductive patterns and the second conductive patterns are electrically connected directly to each other.
Accordingly, the multi chip semiconductor device using such a silicon wiring board reduces stress in connection parts of the metal bumps so as to improve the reliability, improves stability of the connection because of the flatness and dimension precision of the wiring board and makes the increase of wiring density possible at the level a resin wiring board cannot achieve so that miniaturization, a higher density and a higher operational speed can be implemented.
In the above described structure, an insulating layer is formed on the sides so that the sides and the top surface of the substrate form right angles.
In such a structure, the sides of the wiring board can be reinforced and the protection of the conductive patterns on the sides can be improved.
In the above described structure, a resin layer with low stress is provided either or both between the first conductive patterns and the substrate or/and between the second conductive patterns and substrate.
In such a structure, a stress which occurs between the semiconductor chip and the wiring board due to the temperature changes can be relieved so that the reliability of the mounted semiconductor chip can be enhanced.
The process for a semiconductor chip of this invention is characterized by having the step of preparing a semiconductor substrate, the step of forming holes around a peripheral parts of the semiconductor chip units of the semiconductor substrates, the step of forming the first external electrodes on the first plane of the semiconductor substrate and forming the first conductive pattern, in the holes and on the first planes, for making an electrical connection with the first external electrodes, the step of forming inclined planes where the internal angles made up of the inclined planes and the second plane of the semiconductor substrate become obtuse angles and for making the holes penetrate, the step of forming the second external electrodes on the second plane and the step of forming the second conductive patterns for electrically connecting the second external electrodes on the inclined planes and on the second plane with the first conductive patterns.
According to the process for a semiconductor chip of this invention, the inclined planes of which the inner angle made up of the inclined planes and the second plane are obtuse angles and through holes are created between the inclined surfaces and the first surface and therefore, by forming conductive patterns in the through holes, it becomes possible to electrically connect the first plane with the second plane and in addition, it becomes unnecessary to create deep holes and to polish the semiconductor substrate starting from the rear surface so as to make it thinner so that the processing time can be shortened and thereby the cost can be reduced. In addition, the conveyance of the semiconductor substrate is easier in comparison with the thinly processed semiconductor substrates.
The process for a semiconductor chip of this invention is characterized by happening the step of preparing a semiconductor substrate, the step of creating holes around the peripheral parts of the semiconductor chip units in the semiconductor substrate, the step of forming the first insulating layer on the first plane except for on the surface electrodes of the semiconductor substrate and on the inner walls of the holes, the step of forming the first conductive patterns on the first insulating layer and of filling in the first conductive patterns in the holes, the step of forming the second insulating layer with openings for the first external electrodes in parts of the surface of the first conductive patterns, the step of polishing the second plane of the semiconductor substrate so as to be made to have a desired thickness, the step of forming inclined planes, where the inner angles made up of the inclined planes and the second plane are obtuse angles, in border parts between semiconductor chip units in the second plane and of making the holes penetrate to the inclined planes, the step of forming the second conductive patterns electrically connected to the first conductive patterns on the third insulating layer and the step of forming the fourth insulating layer with openings for the second external electrodes in parts of the surface of the second conductive patterns.
According to the process for a semiconductor ship of this invention, the conductive patterns such as electrodes and wires can be formed simultaneously on the semiconductor substrate and the first conductive patterns within the holes can be made to expose from the inclined planes at the same time when the inclined planes wherein the inclined planes and the rear plane form obtuse angles are formed and, therefore, the number of manufacturing steps of the semiconductor chip and the manufacturing cost can be reduced to a great extent.
The process for a semiconductor chip of this invention is a process for a plurality of semiconductor chips gained from a wafer that has the surface on which elements are integrally formed and the rear surface which is opposite to the surface in a parallel manner, including the step of forming a recess around semiconductor chips on the surface, the step of forming inclined planes, where the inclined planes and the surface form acute angles, in the semiconductor substrate, the step of forming the first external electrodes on the surface, the step of forming the second external electrodes on the rear surface, the step of forming the first conductive patterns connected to the first external electrodes within the recess and on the surface and the step of forming the second conductive patterns for connecting the second external electrode with the first conductive patterns on the inclined planes and on the rear surface.
According to the process for a semiconductor chip of this invention, since a recess around the surface and the side surfaces, where the side surfaces and the surface form acute angles, are formed, conductive patterns are formed on the surface and on the rear surface, for example, after forming the first conductive patterns on the top surface of the semiconductor substrate wherein a recess is formed around the top surface, the second conductive patterns are simply formed on the rear surface wherein inclined planes, where the inclined planes and the surface form acute angles, are formed and thereby wires which penetrate from the top surface to the rear surface can be gained and electrodes penetrating from the top surface to the rear surface can be formed easily. Accordingly, chips for multi chip semiconductors can be easily implemented.
The process for a semiconductor chip of this invention is a process for a plurality of semiconductor chip gained from a wafer having the top surface on which elements are integrally formed and the rear surface which are opposite to the top surface in a parallel manner, including the step of forming a recess around a semiconductor chip along the scribe line on the surface of the wafer so as to cross the scribe line, the step of forming the first insulating layer on the inner walls of the recess and on the surface except for the surface electrodes of the semiconductor chip, the step of forming the first conductive patterns by filling in the recess on which the first insulating layer is formed and on the surface on which the first insulating layer is formed in desired forms of wires and electrodes, the step of forming the second insulating layer on the surface with openings for electrodes of the first conductive patterns, the step of polishing the wafer starting from the rear surface so as to be made to be a desired thickness, the step of forming inclined surfaces, where the inclined surfaces and the surface form acute angles, around the rear surface of the semiconductor chip in the rear surface along the scribe line and of making the first conductive patterns within the recess expose from the inclined planes, the step of forming the third insulating layer with openings for the parts of the first conductive patterns exposed from the rear surface and the inclined planes, the step of forming the second conductive patterns on the inclined planes on which the third insulating layer is formed and on the rear surface of the semiconductor chip in the desired forms of wires and electrodes which are connected to the first conductive patterns exposed from the inclined planes and the step of forming the fourth insulating layer formed on the rear surface and the inclined planes of the semiconductor chip with openings for electrode parts of the second conductive patterns.
According to the process for semiconductor chips of this invention, a recess and conductive patterns such as electrodes and wires can be formed at the same time on the wafer and formation of inclined planes in the rear surface so as to form side surfaces where the surfaces and the surface form acute angles, division of the semiconductor chip into pieces and appearance of the first conductive patterns from the rear surface can be carried out simultaneously. Accordingly, the number of manufacturing steps of the chip for a multi chip semiconductor device and the manufacturing cost can be reduced to a great extent.
In the above structure, the step of forming the first external electrodes and the step of forming the first conductive patterns are carried out simultaneously.
In such a structure, the first external electrodes and the first conductive patterns can be formed simultaneously and, thereby, the number of manufacturing steps can be reduced.
In the above structure, the step of forming the second external electrodes and the step of forming the second conductive patterns are carried out simultaneously.
In such a structure, the second external electrodes and the second conductive patterns can be formed simultaneously and, thereby, the number of manufacturing steps can further be reduced.
In the above structure, it is characterized that the step of forming the first layered metal film on the first insulating layer is provided between the step of forming the first insulating layer and the step of forming the first conductive patterns while the step of forming the second layered metal film on the third insulating layer is provided between the step of forming the third insulating layer and the step of forming the second conductive pattern.
In such a structure, electrolytic plating of the conductive pattern and prevention of diffusion of conductive patterns can be implemented by providing a layered metal film in this manner.
In the above structure, the fourth insulating layer is formed by applying a liquid resin which is cured and the substrate is divided into semiconductor chips through dicing. In such a structure, the fourth resin layer is formed by using a liquid resin and thereby the thickness of resin formed on the inclined plates can be secured sufficiently and the conductive pattern can be protected from shock from the outside. In addition, by dividing the resin applied parts through dicing, mechanical and thermal shock due to cutting resistance or the like at the time of dicing can be absorbed by resin, occurrence of inconvenience such as chipping can be prevented and the semiconductor substrate in the condition where a variety of films are formed on the entire surface can be processed at a high speed into semiconductor chip units in a stable condition.
In the above structure, the step of forming inclined planes where the inner angles made up of the inclined planes and the second surface are acute angles on the edge parts of the second plane and of making the holes penetrate to the inclined planes is characterized by being carried out through bevel cutting starting from the second plane.
In such a structure, inclined planes are easily formed in a short period of time and the first conductive patterns can be exposed.
The above structure is characterized in that the etching rate of the third insulating layer is larger than the etching rate of the first insulating layer and the second insulating layer.
In such a configuration, after forming the third insulating layer on the entire surface of the second plane and the inclined planes, the first conductive patterns are exposed and, therefore, the first insulating layer is hardly etched at the time when openings are created in the third insulating layer through etching and the third insulating layer can be selectively etched so that openings are created and, therefore, the first insulating layer, which insulates the first conductive patterns from the semiconductor substrate, is not partially removed.
In the above structure the recess is a trench formed through dicing.
In such a structure trenches can be formed simultaneously in a short period of time in a wafer condition so that the number of manufacturing steps and manufacturing cost can be reduced.
The process for a wiring board of this invention is characterized by comprising the step of forming holes in the surface of a silicon substrate, the step of forming first conductive patterns on the surface and in the holes, the step of forming inclined planes wherein the inclined planes and the rear surface of the silicon substrate form acute angles in the regions enclosing the border parts for the substrate piece units on the rear surface and of making holes penetrate through so as to expose the first conductive patterns and the step of forming the second conductive patterns electrically connected to the first conductive patterns on the rear surface and on the inclined planes.
According to the process for a wiring board of this invention, the holes are made to penetrate by forming inclined planes in the rear surface of the wiring board and, thereby, processing time for the holes can be shortened and the processing cost can be reduced.
The process of a wiring board of this invention includes the step of forming first conductive patterns made up of at least one layer for mounting and wiring electronic parts on the surface of a silicon wafer, the step of forming second conductive patterns made up of at least one layer having electrodes for being mounted on a mother board on the rear surface of the silicon wafer, the step of forming side surfaces by dividing the silicon wafer into pieces of silicon substrate and the step of forming the third conductive patterns on the side surfaces for electrically connecting the first conductive patterns and the second conductive patterns and is characterized in that the step of forming side surfaces by dividing the silicon wafer into pieces of silicon substrate is carried out after the step of forming the first conductive patterns and, after that, the step of forming the second conductive patterns and the step of forming the third conductive patterns are carried out simultaneously.
According to the process for a wiring board of the present invention, a wiring board made of silicon can be gained which has first conductive patterns on the top surface for mounting and wiring electronic parts and the second conductive patterns on the rear surface comprising electrodes for being mounted on a motherboard so that these first conductive patterns and second conductive patterns are electrically connected through the third conductive patterns formed on the side surfaces. In addition, a multi-chip semiconductor wiring board which has surface electrodes and rear surface electrodes electrically connected via the conductive patterns following the side surfaces can be easily implemented. Furthermore, after the step of forming the first conductive patterns, the step of forming side surfaces by dividing the silicon wafer in pieces of silicon substrate and, after that, the step of forming the second conductive patterns and the step of forming the third conductive patterns are carried out simultaneously and, therefore, the number of manufacturing steps can be reduced.
A process for a wiring board of this invention includes the step of forming a recess around the surface of a silicon substrate in a wafer condition, the step of forming the first conductive patterns comprising at least one layer that has electrodes on the surface and within the recess, the step of forming inclined planes wherein the inclined planes and the surface form acute angles on the silicon substrate, the step of forming the second conductive patterns comprising at least one layer that is electrically connected to the first conductive patterns and has electrodes on the rear surface and on the inclined planes of the silicon substrate.
According to the process for a wiring board of this invention, a wiring board which has the first conductive patterns on the top surface and the second conductive patterns on the rear surface and wherein the first conductive patterns and the second conductive patterns are directly electrically connected can be gained. In addition, since a recess and side surfaces wherein the side surfaces and the top surface form acute angles are formed in the wiring board, wires penetrating from the top to the rear can be formed simply by forming conductive patterns on the top surface and on the rear surface. In addition, a wiring board for multi-chip semiconductors which has surface electrodes and rear surface electrodes which are electrically connected via conductive patterns following the side surfaces can be easily implemented from a silicon substrate in a wafer condition.
The above described structure includes the step of forming an insulating layer on the inclined planes so that the insulating layer and the surface of the silicon substrate form right angles and is characterized in that the insulating layer is formed by applying a liquid resin which is cured and divided into pieces through dicing.
In such a structure, a liquid resin is supplied to the inclined planes and the cured resin part is divided into substrate pieces through dicing and, thereby, the resin absorbs mechanical interference and distortion due to heat created by friction occurring because of cutting resistance at the time of dicing so that disadvantages such as chipping can be prevented.
The above described structure is characterized by providing the step of forming a resin layer of low stress between the substrate and the first conductive patterns or between the substrate and the second conductive patterns.
In such a structure, stress due to temperature change occurring between the semiconductor chips and the wiring board can be relieved so as to enhance the reliability of the mounting of semiconductor chips.
A semiconductor device of this invention has a semiconductor substrate, the first external electrodes formed on the first plane of the semiconductor substrate, the second external electrodes formed on the second plane of the semiconductor substrate and through holes formed in the semiconductor substrate and is characterized in that the through holes are provided on inclined planes formed so that the inner angles made up of the inclined planes and the second plane are obtuse angles and as for the first external electrodes and the second external electrodes a plurality of semiconductor chips which are electrically connected through conductive patterns formed so as to follow the inner walls of the through holes and on the inclined planes are layered on each other with the respective first external electrodes and second external electrodes being electrically connected.
According to the semiconductor device of this invention semiconductor chips which have first external electrodes and second external electrodes connected via conductive patterns formed on the inner walls of the through holes and on the inclined planes are layered on each other and a semiconductor device can be gained wherein respective semiconductor chips are electrically connected via the electrodes on both sides of the semiconductor chips so that the semiconductor chips are not arranged in a plane on the wiring board and, therefore, the mounting area can be made small. In addition, since it is not necessary to provide electrodes for connecting metal wires, it is possible to layer two or more semiconductor chips of the same size or of different sizes in a desired order and it becomes possible to make the wire length between respective semiconductor chips short and to make the thickness of the layers small so that a semiconductor device which can achieve miniaturization, high density and a higher operational speed can be implemented.
A semiconductor device of this invention has a semiconductor substrate, first external electrodes formed on the first plane of the semiconductor substrate, second external electrodes formed on the second plane of the semiconductor substrate and through holes created in the semiconductor substrate and is characterized in that the through holes are provided in the inclined planes formed so that the inner angles made up of the inclined planes and the second plane form obtuse angles and as for the first external electrodes and the second external electrodes, between the two first semiconductor chips electrically connected through the first conductive patterns formed so as to follow the inner walls of the through holes and the inclined planes, a second semiconductor chip is provided wherein third external electrodes formed on the parts other than element formation regions on the third plane and the fourth external electrodes formed on the parts other than the element formation regions on the fourth plane are electrically connected through the second conductive patterns so that the first semiconductor chips and the second semiconductor chip are electrically connected directly or via connection members. According to the semiconductor device of this invention, a multi-chip type semiconductor device can be implemented which has a small mounting area, a short wiring length between respective semiconductor chips, a low height of layers and achieves miniaturization, high density and a higher operational speed.
The semiconductor device of this invention is a multi-chip type semiconductor device wherein a plurality of semiconductor chips made of semiconductor substrates wherein elements are integrally formed on the surfaces are layered and the layered semiconductor chips are made of semiconductor substrates which have top surfaces, rear surfaces opposite to the top surfaces in a parallel manner, inclined planes formed so that the inclined planes and the top surfaces form acute angles and recesses formed around the top surfaces and have first external electrodes formed on the top surfaces, second external electrodes formed on the rear surfaces and conductive patterns for connecting the first external electrodes and the second external electrodes formed in the recesses and on the side surfaces and are characterized in that the semiconductor chips are electrically connected to others semiconductor chips via the first external electrodes and the second external electrodes.
According to the semiconductor device of this invention, semiconductor chips which have first external electrodes and second external electrodes connected via conductive patterns are layered and respective semiconductor chips are electrically connected via the first external electrodes and the second external electrodes and, therefore, the plurality of semiconductor chips are not arranged in a plane on a wiring board so that the mounting area becomes small and it is possible to layer semiconductor chips of the same size and, in addition, it is possible to layer semiconductor chips of different sizes in a desired order and a multi-chip semiconductor device can be implemented which has a short wire length between respective semiconductor chips, a low height of the layers, two or more semiconductor chips layered and which can achieve miniaturization, higher density and higher operational speed. In addition, since the semiconductor substrates have inclined planes formed so that the inclined planes and the top surfaces form acute angles and recesses created around the peripheries of the top surfaces, the manufacturing of the semiconductor chips can be carried out easily.
In the above described structure, a semiconductor chip is electrically connected directly or via connection members to a semiconductor chip directly above or to a semiconductor chip directly below through the connection of the mutual electrodes of the semiconductor chips.
In such a structure, a multi-chip semiconductor device can be gained wherein semiconductor chips are connected to each other so as to make the wire length short and make the height of the layers low within the area of a semiconductor chip. Accordingly, a multi-chip semiconductor device can be realized which has a small mounting area, a short wiring length between respective semiconductor chips and a low height of the layers and which achieves miniaturization, higher density and higher operational speed.